Many popular electronic devices, such as mobile telephones and other mobile communication devices, rely on integrated circuits (ICs) for their operation. As those electronic devices become ever more sophisticated while often concurrently being reduced in size, IC density and packaging become increasingly important design constraints. In response, newer packaging solutions have been developed. One packaging solution uses a wafer level packaging technique in which deposition of surface passivation layers, formation of post-fabrication redistribution layers, and solder bumping, for example, are performed on a processed wafer, prior to singulation of the wafer.
In a conventional wafer level packaging process, each surface passivation layer is typically applied using a spin coating process. Lithographic masks are usually then employed to pattern the passivation layers for formation of the post-fabrication redistribution layers, as well as for any desired under-bump metallization. As a result, the conventional process is time consuming, expensive, and often includes several chemical processing steps in which reagents capable of causing significant environmental harm are utilized.